Run the parport2k.exe file (available in C: Actel FlashPro v3.1 FlashPro v3.1) in order to install the parport2k.dll properly (as shown in Figure 3 below). Figure 3: Click the parport2k.exe file to install the partport2k.dll file. We will fix the issue in a future release of FlashPro. Xiamen AcTEC Electronics Co., Ltd. No.4, Tongfu Road, Tong’an District, Xiamen, China.
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Clocking
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The internal clock network of the Smarfusion devices includes a large amount of possible configuration combination. The network has 3 different input clocks (CLKA, CLKB and CLKC), each of them can be connected to a different clock source such as the main oscillator, the RC oscillator, the FPGA fabric or the dedicated single-ended or differential IO. The clock network has an internal PLL and 3 global output clocks (CLKGA, CLKGB and CLKGC). The cortex-M3, digital and analog peripherals clocks are derived either from CLKGA or CLKGC through the NGMUX. Due to the large amount of configuration parameters, it is recommended to use the Actel MSS configuration tool to setup the clock network and let the system boot handle the configuration. However, the eCos HAL includes all the required options to setup the clock network. Note that only a limited subset of combinations have been tested.
SPI bus
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The Actel AF2xxx microcontroller family has 2 SPI buses available. Each SPI bus has a certain number of slave select line (called SPI_x_SSx) that are directly driven by the SPI controller. The first SPI bus has 4 slave select lines available (SPI_0_SS0 to SPI_0_SS3) while the second bus has 8 of them (SPI_1_SS0 to SPI_1_SS7). In addition, the eCos SPI driver allows using the GPIO of the microcontroller as slave select lines which is in some cases required. In the rest of this chapter, the former case is called SPI controlled slave select while the later is called GPIO controlled slave select
NOTE: The SPI_x_SSx microcontroller dedicated pins can be used as GPIO, thus, it is possible to use SPI_0_SS0 as slave select either in SPI or GPIO controlled mode. This is true for all SPI_x_SSx pins.
New SPI devices are instantiated using the following macro:
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NOTE: _csup_dly_ and _csdw_dly_ are only valid when GPIOs are configured to drive the slave select line. When the SPI controller drives the slave select line itself, the user has no control over the exact timing.
The Actel Smartfusion board features a SPI serial flash (AT25DF641) attached to the first SPI bus. The SPI flash is connected to the SPI_0_SS0 line, however, to suit eCos SPI transaction, the line is configured as a general purpose IO and controlled by the SPI driver.
The following section describes how the SPI serial flash is declared. The code is located in devs/fash/cortexm/a2fxxx/a2f200_eval/flash_a2f200_eval.c. The required includes are:
The device is defined to be connected on SPI bus 1, using GPIO 19 for slave select. The Motorola protocol (mode 0) is selected with a bus clock speed of 25MHz.
From the default CDL, SPI bus 1 uses the DMA channel 0 for outbound and channel 1 for inbound transfer. SPI bus 2 uses DMA channel 2 and 3 respectively. The DMA channel number are selected with:
I2C bus
The Actel microcontroller family has 2 I2C buses available and the Smartfusion evaluation kit feature an OLED display connected to the first I2C bus with address 0x3C. The I2C driver is tested using the OLED display, however, the OLED driver is not part of the eCos HAL. A new I2C bus is instantiated using the following macro:
The following section describes how the I2C bus 0 is declared. The code is located in hal/cortexm/a2fxxx/a2f200_eval/current/src/platform_i2c.c. The required includes are:
The first part declares the I2C bus 0 and the second part attached a I2C device with address 0x3C to the bus.
Ethernet Controller
The Ethernet MAC layer of the Actel device is compliant with the RMII 10/100Mbps specification. The development kit interface the DP83848 PHY from National Semiconductor.
NOTE: To use the Ethernet interface of the evaluation kit, the FPGA fabric must be programmed. The Ethernet PHY input clock (50MHz) is connected to an IO only accessible from the fabric. It is therefore required to route the MAC_CLK from the clock network to the IO (T6).
Some of the driver configuration parameters accessible from the CDL file are:
Selecting this option will cause the Ethernet driver to print status messages as various Ethernet operations are undertaken. This is option is designed to help debugging the Ethernet driver.
Selecting this option will set the Ethernet MAC in promiscuous mode, all Ethernet packets will be delivered to the application layer whether or not destinated to the device.
This option specifies the size of the internal transmit buffers used for the Ethernet device.
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This option specifies the size of the internal receive buffers used for the Ethernet device.
This option specifies the number of output buffer packets to be used for the Ethernet device.
This option specifies the number of input buffer packets to be used for the Ethernet device.
Selecting this option will cause the Ethernet driver to accumulate statistics provided from the MAC layer.
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Serial
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The Actel A2Fxxx uses the 16x5x generic serial device driver. The driver is instantiaced through the CYGPKG_IO_SERIAL_CORTEXM_A2FXXX serial package.
DMA
The eCos HAL offers some basics routines to configure and use the 8 DMA channels available in the Smartfusion chips. It must be noted that all channels are sharing the same interrupt. The current implementation limits the transfer size to byte tranfer ( field TRANSFER_SIZE from the CHANNEL_x_CONTROL register ). Currently only the SPI driver makes use of the DMA interface.
DMA channels are registered / released with
DMA channels are configured with
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DMA transfer are initiated using
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DMA interrupts are cleared with
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